(1) Field of the Invention
The present invention relates to a voltage measuring circuit for detecting an unknown voltage in a semiconductor integrated circuit, which has less power source voltage dependency, temperature dependency, and in which a desired detected voltage value can be varied by changing data in an internal memory element.
(2) Description of the Related Art
In electrically erasable programmable read-only memories (EEPROMs) or flash EEPROMs operated by a single power source, it is very important for the control of a cell threshold value after writing to select suitably an internally produced high programming voltage. Further, it is required that such a programming voltage is stable even under any circumstance, and it is desirable to be in dependency upon temperature variations and power source voltage variations. Simultaneously, this programming voltage has to have a high current supply capability so that it does not cause a voltage drop due to a programming current or an increasing parasitic leak current under high temperature conditions.
If there is a large dispersion among devices in several conditions upon manufacture, for example, in tunneling oxide film thickness or in tunneling area when a tunnel current running through an oxide film between a floating gate and a substrate is used for writing, the programming high voltage has to be adjusted respectively to a suitable value corresponding to the dispersion.
In order to satisfy the above-conditions, a powerful charge-pump circuit has been usually used as a voltage boosting circuit. In this system, a voltage measuring circuit determines whether the pumped-up voltage is at a suitable desired value or not, and if it exceeds the desired value, the pumping operation of the charge pump circuit is stopped.
Conventionally, for example, U.S. Pat. No. 4,952,821 discloses such a kind of the art. The arrangement disclosed in this publication will be explained with reference to the drawings.
FIG. 2 is a circuit diagram illustrating an example of conventional voltage measuring circuits.
This voltage measuring circuit has an input terminal 1a at which a voltage Vg to be measured is internally pumped up. The capacitors 1, 2 are connected in series through a floating node N1 to divide the voltage Vg to be measured. Further, an N-MOS 3 for a reset operation is connected to the node N1 and to one end of capacitors 4 to 6 forming a predetermined capacitance ratio. Further, the other ends of the capacitors 4 to 6 are connected to a desired value setting section 10.
The desired value setting section 10 is a circuit for setting a desired value of the voltage Vg to be measured in accordance with three bit data D1, D2, D3 stored in an internal memory element. The section 10 is composed of N-MOS transistors 11 to 16 as switching elements, and inverters 17 to 19. Further, the node N2 connected to the N-MOS 11 to 13 is connected to the output of a constant voltage circuit 20 for generating a reference voltage and to a differential amplifier 30.
The differential amplifier 30 has its input terminals connected to the node N1 and to the node N2, and is a circuit for amplifying a voltage difference between the nodes N1, N2, and for delivering an output signal OUT as a digital value from its output terminal 30a.
Further, the input terminal 1a is connected to a charge pump circuit (not shown) for generating the voltage Vg to be measured, and which has a function of controlling the pumping operation (or voltage boost-up operation) in response to an output signal OUT.
Explanation will be made of operation.
The input voltage Vg to be measured is divided into a voltage ratio between the capacitors 1, 2, to generate a voltage value near to the reference voltage from the constant voltage circuit 20. Meanwhile, a ground level given by data D1, D2, D3 having level "H", or a reference voltage level by data D1, D2, D3 having level "L" is fed to the node N2, selectively Further, when the voltage level of the node N1 exceeds that of the node N2, the differential amplifier 30 delivers the output signal OUT in "L" level from its output terminal 30a.
For example, when the voltage Vg to be measured increases up to a desired voltage, the voltage level of the node N1 exceeds that of the node N2. As a result, the output signal OUT in level "L" is delivered from the output terminal 30a. Accordingly, the pumping operation of the charge pump circuit is stopped. When the level of the voltage Vg to be measured lowers, the voltage level of the node N1 is below the voltage of the node N2. As a result, the output signal OUT is turned into level "H" so as to reinitiate the pumping operation. After such an operation is repeated, the voltage Vg to be measured is stabilized around the desired value.
With the use of the above-mentioned circuit, the detection level of the voltage Vg to be measured is less of dependency upon temperature and power source voltage. Since a completely linear relationship is maintained with respect to the reference voltage, whereby it is possible to obtain a stable operation.
However, the above-mentioned voltage measurement circuit has offered the following problems:
During the operation, in such a case that the node N1 is in a floating condition, if the insulation around the conductor of the node N1 is insufficient, a charge leaks from the node N1, so that the voltage Vg to be measured is shifted from a desired value. In particular, since the flash type EEPROM erases all data therein, the erasing time is longer than that of the EEPROM, and the floating condition is sustained longer correspondingly. Accordingly, the possibility of leakage of charge from the node N1 increases. Further, when the data is erased at a high temperature, the possibility of leakage of charge increases.